Processor startup sequence

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Smiley
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Processor startup sequence

Post by Smiley » Sat Feb 14, 2009 6:06 pm

I've been reading http://www.nondot.org/sabre/os/files/Bo ... pping.html and it says that the processor boots in real mode and sets the CS segment to F000 and EIP to FFF0. It then goes on to say that the processor therefore starts executing code at FFFFFFF0. This makes no sense whatsoever to me. Unless I'm missing something, the processor should start executing at FFFF0 according to the segment addressing scheme with the above CS and EIP values within real mode. If the processor is in real mode, then it shouldn't even be able to access such a high memory address, and yet I've read some texts that say the processor starts execution at FFFFFFF0 and some say the execution starts at FFFF0.

So does anyone know which one is correct? I would really appreciate it if someone gave me an Intel citation that would set the answer in stone.

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IceDane
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Re: Processor startup sequence

Post by IceDane » Sun Feb 15, 2009 2:18 am

You have to understand memory segmentation in order to understand what he's saying there.

Do a search for The Art of Assembly, an old guide to assembly, and you will find everything you need to understand those low level mechanics.

Smiley
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Re: Processor startup sequence

Post by Smiley » Sun Feb 15, 2009 12:32 pm

The next operation to execute should be at location CS:IP or F000:FFF0. The absolute address can be calculated by segment*0x10 + offset or in this case: 0xF000 * 0x10 + 0xFFF0 = 0xF0000 + 0xFFF0 = 0xFFFF0. Either I've done something wrong or the text is wrong.

abcdef
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Re: Processor startup sequence

Post by abcdef » Sat Apr 18, 2009 12:20 am

keep reading the guide you have
0H. Thus, execution begins at address FFFFFFF0H, sixteen bytes from the top of physical memory, in an EPROM. The EPROM is usually located at a much lower physical address, but is being remapped to a high address by the system chipset (e.g. Intel 430HX). Note that the selector/base correspondence here is not the usual relationship when programming in real mode. Typically, in a PC this EPROM will set up a real-mode IDT and jump to the BIOS.

Smiley
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Re: Processor startup sequence

Post by Smiley » Sat Apr 18, 2009 12:46 pm

I still don't understand this even though I've gained more insight into the subject since I posted this. First I don't know what IDT is, a search on Google doesn't seem to be helping me.

Second, after reading a little bit more I've found out the the Motherboard's BIOS' ROM and IBM Cassette BASIC ROM are found at F0000-FFFFF. This may very well be the address region that the BIOS ROM is remapped into that the text is talking about but this also suggests that execution still starts at FFFF0 regardless of whether this address is remapped or not. Sure the chipset may be converting this address to something else but as far as the processor is concerned it is executing at address FFFF0, not FFFFFFF0.

The text does say "Note that the selector/base correspondence here is not the usual relationship when programming in real mode." but the text doesn't elaborate on this which doesn't give me much faith in the text.

abcdef
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Re: Processor startup sequence

Post by abcdef » Sat Apr 18, 2009 6:47 pm

Smiley wrote:I still don't understand this even though I've gained more insight into the subject since I posted this. First I don't know what IDT is, a search on Google doesn't seem to be helping me.

Second, after reading a little bit more I've found out the the Motherboard's BIOS' ROM and IBM Cassette BASIC ROM are found at F0000-FFFFF. This may very well be the address region that the BIOS ROM is remapped into that the text is talking about but this also suggests that execution still starts at FFFF0 regardless of whether this address is remapped or not. Sure the chipset may be converting this address to something else but as far as the processor is concerned it is executing at address FFFF0, not FFFFFFF0.

The text does say "Note that the selector/base correspondence here is not the usual relationship when programming in real mode." but the text doesn't elaborate on this which doesn't give me much faith in the text.
idt = interrupt descriptor table

its an array whose type is defined in the intel manuals (http://www.intel.com/products/processor/manuals/) and allows the processor to handle interrupts. if you are familar with linux assembly programming and used int 0x80 to make system calls that really expands to INTERRUPT 0x80 which will get the function pointer out of the 0x80 entry in the IDT. it then uses this function to handle the interuppt.

you really need to read the intel manuals to learn how all the hardware works and how the operating system interacts with it. Like i said before read osdev.org forums and wiki as much as you can, and you can ask questions here and i will try to answer

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